1. Field of the Invention
The present invention relates to a semiconductor device, in particular, relates to clock failure detection within a semiconductor device.
2. Description of the Related Art
Recently, single-chip microcomputers, within which a CPU (central processing unit) and other circuits, such as memories, are monolithically integrated, are widely used. A single-chip microcomputer incorporates an oscillator circuit for developing a system clock of a desired frequency. Other circuits within the single-chip microcomputer are designed to operate in synchronization with the system clock. When the frequency of the clock is in a specific frequency range defined by the specifications, the single-chip microcomputer operates normally. However, the single-chip microcomputer may malfunction if the frequency of the clock generated by the oscillator circuit is out of the specific range.
Japanese Laid Open Patent Application JP-A-Heisei 07-6155 discloses a technique for avoiding malfunctions of a single-chip microcomputer by detecting fail of an oscillator circuit incorporated therein. FIG. 1 illustrates a block diagram illustrating a configuration of a clock generator circuit disclosed by this document. A clock generator circuit 101 supplies a system clock to a CPU (not shown) and peripheral devices (not shown) within a microcomputer 100. As shown in FIG. 1, the clock generator circuit 101 is configured with a sub-clock oscillator circuit 102, a main clock oscillator circuit 103, a timer 104, an OR circuit 105, a clock switch flag register 106, an oscillation control flag register 107, a timer reset flag register 108, and a system clock switching circuit 109. The registers 106 to 108 are connected to an internal bus 121.
In the clock generator circuit 101, the timer 104 receives a sub-clock signal 111 developed the sub-clock oscillator circuit 102 on the clock signal input, and the OR circuit 105 receives a timer carry signal 116 outputted from the timer 104 and a system reset signal 113 outputted from a reset control circuit to develop a flag reset signal 117. The flag reset signal 117 is the logical OR of the timer carry signal 116 and the system reset signal 113. The system clock switching circuit 109 generates the system clock signal in response to the output of the main clock oscillator circuit 103.
When a failure occurs in the main clock oscillator circuit 103, the generation of a main clock signal is stopped, and therefore the clock generator circuit 101 stops supplying the system clock signal to the CPU within the microcomputer 100. Consequently, the CPU stops operating. The conventional microcomputer 100 detects the failure in the main clock oscillator circuit 103 on the basis of the fact that the operation of the CPU is stopped. When detecting the failure of the main clock oscillator circuit 103, the conventional clock generator circuit 101 automatically switches the clock oscillator circuits 102 and 103 to generate that the system clock signal using the output of the sub-clock oscillator circuit 102. As a result, the operation of the microcomputer 100 is maintained.
As shown in FIG. 1, the clock generator circuit 101 is provided with input terminals 131 to 134 to be connected to externally-provided oscillators. The system clock is generated to have a natural frequency of the oscillators. The generated system clock is supplied to the CPU, the memory, and peripheral circuits of the microcomputer 100. In other words, the oscillator circuit generates the clock having the constant frequency mentioned above, in response to the signal supplied from the input terminal.
One issue is that application of an external force to the single-chip microcomputer may cause deformation of the input terminals 131 to 134, and thereby cause short-circuiting or incomplete short circuiting. Also, in the case where the microcomputer 100 is mounted on a substrate, short-circuiting or incomplete short-circuiting may be caused by poor contacting with the substrate. Short failures are often caused by physical factors, and it is therefore extremely difficult to avoid short failures related to the input terminals.
If any two of the input terminals are short-circuited, the frequency of the system clock generated by the clock generator circuit 101 may be out of the allowed frequency range. This may cause runaway of the CPU within the single-chip microcomputer, read and/or write errors of the memory, and other undesirable improper operations.
FIG. 2 is a table showing causes of the failures, and the statuses of the resultant outputs of the clock generator circuit. The causes of the failures are listed on the left column, and the statuses of the resultant outputs are listed on the right column.
As shown in FIG. 2, short-circuiting (or incomplete short-circuiting) at the input terminals of the clock generator circuit may result in that the clock generator circuit does not develop a clock signal of a desired frequency; the output of the clock generator circuit may be fixed to the power supply potential VDD or the earth potential GND.
With reference to the bottom row of the table, one failure mode that the inventor has discovered is that the clock generator circuit oscillates unstably and the output thereof undesirably includes high frequency components in the frequency range above the frequency of the clock signal normally developed by the clock generator circuit, when two of the input terminals are short-circuited through a parasitic inductive element.
In the conventional system, consideration is not given to the fact that a clock signal containing high-frequency components may be outputted from the oscillator circuit. With the above conventional technique, therefore, it is difficult to deal with such failure mode in which a clock signal containing high-frequency components is generated. This problem is desirably solved immediately.